Blue Pearl Software’s Version 4.0 of Cobalt Timing Constraint Generation™ Speeds-Up Timing Closure

SANTA CLARA, California – November 18, 2008 – Blue Pearl Software™, Inc. released Version 4.0 of its Cobalt Timing Constraint Generation™ solution. This new release of Cobalt expands the tool’s capabilities to include improved generation of multi-cycle paths in a bottoms-up block level flow, enhanced Synopsys design constraints (sdc) checking, and improved common clock divider recognition. In addition to handling register transfer level (RTL) designs, Cobalt 4.0 offers enhanced support for gate-level designs.

Cobalt Timing Constraint Generation automates the very difficult problem of creating false and multi-cycle path timing exception constraints at the RTL. Cobalt creates a comprehensive set of sdc constraints at the critical, early stage of RTL coding within minutes to hours.

New Cobalt Capabilities

To close timing, many designers are resorting to designing in multi-cycle paths that take three or more cycles to complete their operations. Unlike other tools that are not able to calculate the actual number of cycles required for path operation, Cobalt employs proprietary and optimized Symbolic Simulation technology to accurately determine the actual minimum number of clock cycles required for multi-cycle path operation. Release 4.0 provides greater support for blocklevel and pipe-lined design by allowing customers to define information about the behavior of control signals that drive block ports. This allows Cobalt to generate multi-cycle path constraints that would not otherwise be possible to create because the control is generated by another block Blue Pearl Software 4677 Old Ironsides Drive, Suite 430 Santa Clara, CA 95054 408.961.0121 or chip. This unique and powerful feature allows fast block level runs to identify all multi-cycle path constraints in the block. In addition, Cobalt’s effortless migration of constraints between the block and top levels, and vice-versa, saves design time and lowers design risk.

Cobalt 4.0 also offers improved clock generation logic processing that automatically recognizes common clock dividers and is able to determine the divide by factor to generate accurate internal clock constraints.

In addition, Cobalt now offers enhanced sdc checking that enables identification of errors in manually created sdc files. While Cobalt’s ability to generate constraints at RTL, prior to synthesis, offers the greatest benefits in increased design productivity, Cobalt 4.0 also offers improved support for complex user-defined primitives and so facilitates enhanced timing constraint generation for gate-level designs.

“Increasingly larger and more complex designs are pushing the limits of area, power, and performance. With multiple clocks, and multiple modes caused by low power requirements, routing congestion increases, and it gets more difficult to optimize for performance, increasing the necessity for automation of timing constraint generation,” stated Bill Alexander, VP of Marketing for Blue Pearl Software. “Cobalt is integrated with all leading EDA tool flows and its new features facilitate faster timing closure, improve its overall usability and help reduce design risk by preventing the introduction of errors in the process. This makes using Cobalt easier, more accurate, and more reliable than using other methodologies or tools.”

About Blue Pearl Software

Headquartered in Santa Clara, Calif., Blue Pearl Software is a privately-held electronic design automation (EDA) company committed to automating timing closure, reducing iterations in digital design flows, and improving design productivity.

For the latest news and information on Blue Pearl Software and for evaluation of Indigo RTL Analysis, Cobalt Timing Constraint Generation and Azure Timing Constraint Validation software, visit www.bluepearlsoftware.com.

Bill Alexander
408-961-0121, ext. 302