Blue Pearl Software Announces Azure Timing Constraint Validation

SANTA CLARA, California – March 31, 2008 – Blue Pearl Software™, Inc. announced the release of Azure Timing Constraint Validation™, which automatically validates timing exception constraints at all stages in the design flow from RTL to final netlist. This breakthrough new verification solution allows chip designers to automatically check the timing constraints used to direct synthesis, static timing analysis and place & route tools to meet chip timing, power and area targets. Azure ensures that the timing constraints used are valid and accelerates timing closure. The huge increase in design constraint file sizes results in designers spending significant effort and time to ensure that their constraints are valid. Manual constraint validation is extremely error-prone and invalid constraints can result in design iterations and re-spins. Azure drastically reduces design risk by automatically validating constraints.

Azure is based on World Class State-Space Search Technology

Azure Timing Constraint Validation is based on industry leading state-space search technology that has been used in production by several leading semiconductor companies. Competing tools based on traditional formal verification technologies, use combinational analysis techniques. These techniques can’t validate multi-cycle paths and result in the incorrect reporting of paths that are sequentially false. Azure’s innovative technology is superior since it offers full sequential analysis of false and multi-cycle paths.

In addition to validating user specified constraints, Azure can validate constraints automatically generated by Blue Pearl’s Cobalt Timing Constraint Generation™ software. Cobalt uses innovative symbolic simulation technology to generate timing exceptions that significantly improve quality of results (QoR).

Blue Pearl’s proprietary innovative technologies work at both the gate and RT level. They are optimized for RT Level descriptions and can take advantage of the design knowledge defined at this high abstraction level. “These breakthrough technologies allow Blue Pearl Software to provide the highest performance, industry leading, capabilities in RTL checking, timing constraint generation and timing constraint validation,” said Ellis Smith, CEO of Blue Pearl Software.

Azure Integrated with Leading Vendor Tools

Azure Timing Constraint Validation is integrated with all leading EDA tool flows. Azure reads industry standard Verilog design descriptions and industry standard SDC files. Azure produces industry standard assertions in Property Specification Language (PSL) and System Verilog Assertions (SVA). These assertions can be used in both simulation and debugging tool environments to increase design confidence.

Using Azure to automatically validate SDC timing constraints significantly reduces design risk and results in large reductions in design cycle times. Higher quality constraints can also greatly improve QoR. Azure provides huge time savings and lower development costs over traditional time-consuming and error-prone manual verification techniques.

Azure Timing Constraint Validation is available now for a one year time based license price of $95,000.

About Blue Pearl Software

Headquartered in Santa Clara, Calif., Blue Pearl Software is a privately-held electronic design automation (EDA) company committed to reducing iterations in digital design flows and improving design productivity. For the latest news and information on Blue Pearl Software and for evaluation of Indigo RTL Analysis, Cobalt Timing Constraint Generation and Azure Timing Constraint Validation software, visit www.bluepearlsoftware.com.

Blue Pearl Software and the Blue Pearl logo are trademarks of Blue Pearl Software, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies.

Bill Alexander
408-961-0121, ext. 302