Blue Pearl Software Introduces Its Cobalt Timing Constraint Generation Software for Reducing Design Iterations and Risks in IC and IP Development 

SANTA CLARA, Calif., July 18, 2006—Blue Pearl Software™, Inc. rolled out its new Cobalt Timing Constraint Generation™ software used in the design of complex integrated circuits (ICs) and intellectual property (IP) blocks. Cobalt reduces the time required to achieve timing closure and improves quality of results (QoR) by automatically generating false and multi-cycle path timing constraints.  Blue Pearl Software is a privately-held electronic design automation (EDA) company.

Download datasheet here.

Higher Productivity, Fewer Iterations With Automatic Generation of Timing Constraints

Achieving timing closure in today’s complex chip designs requires the iterative identification of timing exceptions, and then specifying them as constraints for logical and physical synthesis tools. Timing exceptions are those paths that, while appearing crucial to timing analysis, are actually false or multi-cycle paths that have no affect on clock frequency. Designers typically expend weeks of manual effort to identify these exceptions in an iterative, error-prone process that often results in significant delays in chip development projects.

Blue Pearl Software’s Cobalt Timing Constraint Generation quickly identifies false and multi-cycle paths in full chip designs and chip modules specified at the register-transfer-level (RTL) in synthesizable Verilog. It then automatically generates timing constraints in the Synopsys Design Constraint (SDC) format.

By generating all of the timing-exception constraints at the functional RTL level, Blue Pearl Software’s Cobalt software eliminates optimization of paths that make no contribution to design performance.  In addition, it can eliminate many weeks of error-prone manual effort, improve the QoR and lower the design risks.

Cobalt Timing Constraint Generation generates industry-standard SystemVerilog Assertions (SVA) and Property Specification Language (PSL) assertions. These assertions can be used to independently verify the generated constraints using third-party simulation and formal verification tools. Cobalt Timing Constraint Generation is based on the breakthrough functional RTL technology used in Blue Pearl Software’s Indigo RTL Analysis tool. 

Blue Pearl Software’s Suite of Engineering Productivity Tools

Cobalt Timing Constraint Generation is the newest tool in Blue Pearl’s suite of engineering productivity enhancement tools.  Other products are Indigo RTL Analysis—currently used by many leading edge electronics and semiconductor companies—and Blue Pearl Software’s Azure Timing Constraint Validation software.  Azure is based on new technology that automatically verifies existing SDC timing-exception constraints, and will be available later this year.  Blue Pearl Software tools are developed to work together seamlessly in a single executable program with a user-friendly environment. 

Availability and Pricing

Cobalt Timing Constraint Generation runs on the Solaris, Linux, and Windows operating systems.  It is available now for $75,000 (U.S.) for a one-year, time-based license.


Click here to download a PDF datasheet on Cobalt Automatic Timing Constraint Generation.

About Blue Pearl Software

Headquartered in Santa Clara, Calif., Blue Pearl Software is a privately-held electronic design automation (EDA) company.  It is committed to reducing iterations in digital design flows and improving design productivity at the register-transfer-level.  For the latest news and information on Blue Pearl Software and for evaluation software, visit www.bluepearlsoftware.com.


Blue Pearl Software and the Blue Pearl logo are trademarks of Blue Pearl Software, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies.


Bill Alexander
408-961-0121, ext. 302

Abbie Kendall
Armstrong Kendall, Inc.