Blue Pearl Software to showcase Visual Verification Suite 2019 at the Design Automation Conference

New release features usability updates to help quickly find and fix design issues as well as IEEE 1735 encrypted IP flow to streamline CDC analysis.

SANTA CLARA, California –May 28, 2019 – Blue Pearl Software, Inc., a leading provider of design automation software for ASIC, FPGA and IP RTL verification, will showcase their Visual Verification Suite™ 2019.2 at the 56th annual Design Automation Conference (DAC) next week in Las Vegas.

With the Visual Verification Suite, designers verify as they code. The suite features HDL Creator™ smart editor, Analyze™ RTL advanced static and formal linting, an integrated debug environment, enhanced Clock Domain Crossing (CDC) analysis and automated SDC generation. An integrated Management Dashboard is also provided to track progress and deliver signoff statistics for audits and design reviews.

“Blue Pearl Software Visual Verification Suite enables our engineers to rapidly locate and correct errors, early in the design cycle,” said Patrick West, Senior Electrical Engineer, Digital, GE Healthcare. “It’s user-friendly Linting and CDC capabilities are great for educating newer team members and checking their work. It also finds subtle bugs that can be missed by even the most experienced designers.”

New for the 2019.2 release is enhanced cross probing between the HDL Creator™ smart editor and Analyze RTL™ structural and formal linting as well as enhanced reporting to quickly pinpoint issues and resolve them at their origin. In addition, updates to the graphical user interface and FPGA vendor libraries streamline design setup and analysis.

“We have been using Blue Pearl Software’s Analyze RTL for many years to help us internally verify our commercial IP offerings,” said Brian Small, Senior Design Engineer, Northwest Logic. “With the Visual Verification Suite’s new IEEE 1735 encryption flow support, we can now offer our encrypted IP customers the ability to use Blue Pearl Software tools on their full designs, including analysis of the encrypted IP components.”

Also new for 2019.2 is the ability to read and obfuscate encrypted IP taking advantage of the IEEE 1735 standard. This new flow enables encrypted IP to be used during clock domain crossing analysis.

“With the new IEEE 1735 encryption flow, our partners can provide encrypted IP which enables 100% CDC analysis across a design without exposing their proprietary RTL,” said Ellis Smith, Blue Pearl Software, Chairman and CEO. “This new flow will definitely help our mutual customers find and fix errors faster.”

Attending DAC? Stop by booth 345 and have our experts show you how to verify as you code with the Visual Verification Suite 2019. There will be exciting floor demos, daily Lunch and Learns with industry and Blue Pearl experts. Everyone who attends a demo, private meeting or Lunch and Learn will also receive an HDL Creator t-shirt and a *free 6-month license of HDL Creator.

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About Blue Pearl Software

Blue Pearl Software, Inc. is a leading provider of DO-254 compatible design automation software for ASIC, FPGA and IP RTL verification. Our customers are RTL managers and developers, in military, aerospace, semiconductor, medical, communications and safety critical design companies. The Visual Verification™ Suite speeds block and project level verification with advanced integrated RTL structural and formal linting, constraint generation and clock domain crossing analysis. Our usability is unmatched in the industry and can help your design team accelerate development and produce high reliability designs. The Visual Verification Suite is designed, tested and supported in the United States of America.

* free 6-month HDL Creator license is limited to qualified active FPGA or ASIC students, designers or managers and will be provided within two weeks following DAC.

Press Contact:

Jenn Treiber, Blue Pearl Software, +1- 408.961.0121, x341
jenn.treiber@bluepearlsoftware.com

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