We are excited to announce “Release 6.0 of Blue Pearl Software Suite” which includes comprehensive RTL analysis, clock-domain crossing (CDC) checks, and automatic SDC generation for SoC designs. Blue Pearl Software Suite is easy to use for any level of ASIC/FPGA designers.

Our Software Suite which runs on Windows and Linux, offers multi- language (Verilog, SystemVerilog and VHDL) support, and supports major synthesis flows. Designers can mix and match hardware languages in the same design with language checking that matches downstream tools. Its visualization and validation technology gives immediate feedback for validating its automatically generated timing constraints.

To Learn More

“Click here” to view the Blue Pearl Software Suite page.

Blue Pearl also offers “hands-on workshops” and “online software evaluations”.