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Issue 22: When debugging it’s always either the reset or the clock!

FPGA designs are becoming very complex for many FPGA developers. One thing that often causes issues during integration of IP and proprietary blocks is that of resets and clocks. In this blog we will look at resets and how they are used varies from device to device. Starting with the basics, we use reset to […]

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Issue 21: Using Revision Control Systems with the Visual Verification Suite

Continuous Integration and Continuous Deployment (CI/CD) used in the development of FPGA, ASIC and Intellectual Property cores is a process of build automation and RTL code testing each time the development team makes changes under version control. The practice is focused on improving hardware quality throughout the development life cycle via automation. During the CI/CD […]

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Issue 20: Code Quality, It’s a Matter of Style

Code quality is essential to staying on schedule, avoiding design iterations and worse, bugs found in production. For any design team, creating readable and maintainable code that everyone understands takes some common discipline, starting with the basics such as naming conventions. It’s not so much whether the organization prefers big endian or little endian, spaces […]

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Guest Blog: Using Blue Pearl Software to Find Clock Domain Crossings

Adam Taylor CEng FIET• 1stEmbedded Systems Consultant, FPGA Expert, Prolific FPGA Writer A few weeks ago, we talked about how we could synchronise between clock domains in Vivado, I also noticed a couple of questions on r/FPGA about tools which could be used to find CDCs in designs. So, I thought it might be a […]

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Issue 19: A slogan is just that, a slogan

A slogan is just that, a slogan or sometimes referred to as a tag line. Something catchy, something fresh and, of course, something we hope you don’t forget. So, with Blue Pearl Software’s slogan, ‘verify as you code’, we hope it conjures up a feeling that as you code, a smart editor is keeping watch. […]

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Issue 18: So, what’s a Grey Cell anyway…

They say with a chain, it is only as strong as its weakest link. The same can be said about an EDA tool chain for developing and verifying FPGA and ASIC designs. In fact, one of the most significant challenges in the development of a design is verification, and surprisingly it is not the home-grown […]

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Issue 17: Code Quality Essentials for High Reliability FPGAs – Part 3

When designing FPGAs, code quality is essential to staying on schedule, avoiding design iterations and worse, bugs found in production. This is especially true when it comes to high reliability applications such as automotive, space and medical devices where bugs can be extremely expensive or impossible to fix. But just what makes RTL (VHDL or […]

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Issue 16: Code Quality Essentials for High Reliability FPGAs – Part 2

When designing FPGAs, code quality is essential to staying on schedule, avoiding design iterations and worse, bugs found in production. This is especially true when it comes to high reliability applications such as automotive, space and medical devices where bugs can be extremely expensive or impossible to fix. But just what makes RTL (VHDL or […]

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Issue 15: Code Quality Essentials for High Reliability FPGAs – Part 1

As a young hardware engineer, I started using programmable logic. What could be better, aside from maybe the price and power. You didn’t have to be too disciplined during the design phase because you could just reprogram the device if you had a bug or two. Heck your boss didn’t even have to know, just […]

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Issue 14: Accelerated Verification of Block-Based FPGA Designs

FPGA designers face increasing challenges with time-to-market due to the combination of increased FPGA complexity and performance. This often moves the engineer away from hand crafting each element of the design and toward using IP cores provided by device vendors and other third-party suppliers. Using off the shelf IP frees the engineer to focus on […]

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