Blue Pearl Software – The Next Generation of HDL Creation and Verification
The Visual Verification Suite enables our engineers to rapidly locate and correct errors, early in the design cycle and finds subtle bugs that can be missed by even the most experienced designers.
The ESA soft-cores catalogue was developed to facilitate reuse of existing integrated circuit functions needed onboard satellites. Our contract with Blue Pearl is to verify and improve the quality and usability of the IP for European space programs.
Real-time syntax and style checking inside an intuitive, easy-to-use full featured editor.
Comprehensive static and formal linting and debug for error free, high QoR and quality design.
Guarantees synchronized glitch free designs.
Designing High Reliability FPGAs leveraging
the Visual Verification Suite
Part 1: Introduction to the
Visual Verification Suite
Designing High Reliability FPGAs leveraging
the Visual Verification Suite
Part 2: Verify as you Code
Designing High Reliability FPGAs leveraging
the Visual Verification Suite
Part 3: Avoiding metastability
Designing High Reliability FPGAs leveraging
the Visual Verification Suite
Part 4: You cannot manage
what you don’t measure
