“Create quickly generated timing exception constraints that improved the timing on our design by 30% after synthesis and placement in a Magma flow.”
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“We use Create to generate timing exceptions for our challenging design blocks for Palmchip SoC Platform and IP blocks and have found that Create runs very fast and produces accurate constraints at RTL.”
“At Fujitsu, we use Analyze RTL Analysis from Blue Pearl Software to find bugs in the netlist early when they are easier to fix. From our experience, we can find bugs that could potentially save a tapeout.”