Blue Pearl Software Announces Release 9.1 Featuring New RTL Debugging Environment Including Formal Technology for Clock Domain Crossing (CDC)

Demos at DAC, June 7-11, 2015, Moscone Center, San Francisco, California

SANTA CLARA, California – June 7, 2015 – Blue Pearl Software, Inc., the provider of EDA software that accelerates IP and FPGA verification, announces release 9.1 of its software suite for Windows® and Linux® operating systems. It introduces a new RTL debugging environment that includes formal technology for improved clock domain crossing (CDC) analysis.

“Blue Pearl Software is focused on delivering innovation for design analysis, CDC checking and timing constraints generation,” said Ellis Smith, Chairman and CEO, Blue Pearl Software. “By expanding our debugging capability and adding formal verification based technology, we help customers spend less time writing PERL scripts and more time verifying their RTL designs.”

What’s New in 9.1

Blue Pearl’s new RTL debugging environment helps designers pin point root causes and correct some of the toughest issues to debug.

  • Multi-trace technology – Displays schematic traces from any pin or net in the design to its driving or loading register or port in its logic cone. This helps designers quickly understand the logic that controls or loads a design object.
  • Improved Design Browser – Allows user click and expand through complex hierarchies to look at design objects and see their schematic or RTL. Design search to find location of any instance, cells or port.
  • Live log file – Enables full cross probing of any design object in the log to the design browser location, schematic and RTL.
  • Longest RTL Path View – Reports RTL in critical timing paths to help designers identify problems that cause timing issues such as high fanout or excessive logic in path.
  • Formal Verification based technology – Provides another technique to help designers find additional CDC problems.

To Learn More

Release 9.1 of the Blue Pearl Software Suite will be demonstrated at the Design Automation Conference (DAC), June 7-11, in Booth #832, Moscone Center, San Francisco, California. To reserve a private demo at DAC, please register here.

Price and Availability

Release 9.1 of the Blue Pearl Software Suite is available now. The base product, RTL analysis, starts at $10,000 for a floating 1-YR TBL, with options for CDC and SDC starting at $15,000, and $10,000 respectively. Please contact to arrange a demo, or for additional pricing and upgrade information.

The Blue Pearl Software Suite is also available for online purchase via the Embedded Software Store or the Blue Pearl Software online store. For more information about the online stores, please visit or

For more information about Blue Pearl Software, please visit

About Blue Pearl Software

Blue Pearl Software, Inc. provides EDA software that accelerates IP and FPGA design verification. The company’s Blue Pearl Software Suite checks RTL designs for functional errors and automatically generates comprehensive and accurate Synopsys Design Constraints (SDC) to improve quality of results (QoR) and reduce FPGA design risks.

Visit Blue Pearl Software at


Press Contact:Nancy Chou, Blue Pearl Software, +1- 408.961.0121, x 337