SANTA CLARA, California – May 25, 2016 – Blue Pearl Software,  Inc. a leading provider of design automation software for ASIC,  FPGA and IP RTL verification, today announced the appointment of John Panagiotopoulos, founder of Santorini Consulting Group, its representative for the popular Visual Verification Suite in the US West.

The Visual Verification Suite provides the industry’s fastest bug find / fix rate and features Analyze RTL™ linting and debug, Clock Domain Crossing analysis and automatic SDC timing constraint generation. The suite reduces design cycles and overall development time by identifying RTL issues up-front. It improves design quality of results by identifying coding style and content problems ensuring that there are no hidden metastability issues that could later show up as field failures with potentially disastrous consequences.

With the Visual Verification Suite, Verilog, VHDL and System Verilog designers can also automatically generate an exhaustive set of constraints that address false and multi-cycle paths that are compatible with their choice of synthesis tool. The Visual Verification Suite works with all of the leading ASIC and SoC simulation and synthesis tools, as well as FPGA vendor supplied tools.

“Blue Pearl’s breakthrough verification solutions for accelerating advanced sign-off, proves that the Design Cycle doesn’t have to be painful.” said John Panagiotopoulos. “Blue Pearls products create predictability, reduces time to market, improves results and decreases cost by doing fewer validation and verification iterations post simulation and synthesis”

John Panagiotopoulos founded Santorini Consulting Group in 2015 to bring state-of-the-art EDA tools, IP, and Design Services to the semiconductor industry. With more than 25 years of industry experience, John has held senior management positions at IBM Microelectronics, Samsung System LSI, Kawasaki Microelectronics (acquired by MegaChips Corporation) and eSilicon prior to founding Santorini Consulting Group. “Santorini Consulting Group is passionate about offering the most-optimized solutions to the ASIC / FPGA semiconductor market.”

“John is an EDA veteran, who understands the challenges designers face with today’s processes and tools,” said John Molyneux, COO, Blue Pearl Software. “With the complexity of today’s designs, ease of use and accurate debugging is a necessity in order to meet project timelines. With his experience, I know that John will help provide the rapidly expanding value of the Blue Pearl Software Visual Verification Suite to many new users.”

About Blue Pearl Software

Blue Pearl Software, Inc. is a provider of DO-254 complaint design automation software for ASIC, FPGA and IP RTL verification. Our customers are RTL managers and developers, in military, aerospace, semiconductor, medical, communications and safety critical design companies, who wish to avoid costly and time consuming design spins due to simulation / HW mismatches, invalid constraints and clocking issues.

Visit Blue Pearl Software at https://bluepearlsoftware.com

Press Contact:
Jenn Treiber, Blue Pearl Software, +1- 408.961.0121, x 341
jenn.treiber@bluepearlsoftware.com

John Panagiotopoulos
978-930-0811
JohnP.SA@bluepearlsoftware.com