HDL Creator Accelerates RTL and Test Bench Generation
Blue Pearl’s HDL Creator smart-editor verifies over 2000 syntax and coding standards as you code, reducing time consuming design iterations.
SANTA CLARA, California – Oct 09, 2018 – Blue Pearl Software, Inc., a leading provider of design automation software for ASIC, FPGA and IP RTL verification, today announced public access of its all new HDL Creator™ smart-editor along with a free 14-day trail and promotional offering.
HDL Creator is ideal for developers coding both RTL and test benches who are seeking to enhance productivity, predictability and code quality for complex FPGAs, ASICs, and IP designs. Unlike standard editors such as VI, EMACs and Notepad++, HDL Creator provides advanced real-time analysis to find and fix complex issues, such as compilation and missing dependencies.
In addition, HDL Creator provides over 2000 real-time syntax and company specific coding standards checks along with graphical visualization features to help understand and debug new and legacy code. HDL Creator streamlines HDL development and decreases design iterations through improved initial code quality.
“Since we debuted our new smart-editor at the Design Automation Conference we have been working closely with several early access design teams,” said Ellis Smith, Blue Pearl Software, Chairman and CEO. “By verifying as they code, these teams are reporting decreased iterations through simulation and synthesis. Errors are caught and fixed up front, while coding, not in downstream tools. It just makes sense. Starting with higher quality HLD improves overall productivity.”
HDL Creator is now available both as a stand-alone editor and as part of the Visual Verification Suite. As a special introductory offer, between now and Dec 31st, 2018, for each HDL Creator purchased, Blue Pearl will provide a second license of equal or lesser value for free.
In addition, existing Visual Verification Suite Analyze RTL customers on maintenance will receive a free copy HDL Creator integrated within the 2018.3 release. Visual Verification Suite 2018.3 also features a major upgrade to the Clock Domain Crossing (CDC) analysis. The upgrade features simultaneous clock and reset domain analysis to find and fix potential metastability issues that arise in system that have asynchronous reset de-assertion across clock domains.
Test Drive Today!
To give HDL Creator a test drive, simply download the HDL Creator standalone executable (https://bluepearlsoftware.com/downloads) and request your free 14-day trial license . To try HDL Creator inside the Visual Verification Suite, download the Visual Verification Suite and request a Starter Edition license.
To learn more about HDL Creator and view training videos, please visit https://bluepearlsoftware.com/hdlcreator
About Blue Pearl Software
Blue Pearl Software, Inc. is a provider of design automation software for ASIC, FPGA and IP RTL creation and verification. Its Analyze RTL™ linting and debug, Clock Domain Crossing analysis and Synopsys Design Constraints (SDC) generation solutions are proven to improve quality-of-results (QoR), reduce risk and decrease development time. The Visual Verification Suite complements RTL simulation solutions provided by EDA and FPGA vendors by ensuring code and SDC quality along with clocking integrity. Engineered to maximize RTL error find/fix rates, the Visual Verification Suite uniquely provides easy setup, consistent results, Management Dashboard for complete push-button analytics, and runs on both Linux and Windows.
Jenn Treiber, Blue Pearl Software, +1- 408.961.0121, x341 email@example.com