ASICs and FPGA routinely have millions of gates with memories, transceivers, third party IP and processor cores. Problems can be time consuming and complex to debug in the lab and through simulations. Designers need verification tools that can identify problems quickly to reduce their verification and debug time before simulation, before synthesis, and definitely before burning chips in the lab.
- IEEE Verilog/System Verilog & VHDL language specification compliance and syntax
- User configurable checks along with standard checks, STARC, and Xilinx UltraFast
- GUI to streamline debug; integrated RTL, Schematic, and message viewer
- Easy debug message sorting, filtering and waiving to pinpoint problems
- Flow automation, Command Line Interface (CLI), and re-usable message waiver file
- Decrease learning time with Setup Wizard
Identifies Design Issues Quickly
The Visual Verification Environment enables Analyze RTL™ users to debug design issues quickly using intelligent sorting and message filtering. The key features include low Noise, check customization for specific design style, easy setup, and waiver migration.
RTL Checks for High Speed Designs
It is important to find as early as possible RTL coding that prevents the design from getting desired speed. When designing FPGA’s, because their fabric is more constrained than an ASIC, certain types of structures causes slow downs. Rather than wait for synthesis or static timing analysis results, Analyze RTL™ users can easily identify high fanout nets, deeply nested “if-then-else” statements, excessively long logic paths, and poor reset methodology.
Blue Pearl’s Analyze RTL™ combines the ease-of-use methodology and extensive analysis of super-lint tools with the power of formal verification into a single high performance, high capacity design checking solution. With Blue Pearl, you get a unique combination of powerful built-in checks and formal analysis that gives you the most comprehensive and powerful static design checking capability available. Deploy Blue Pearl early and eliminate complex design errors at all stages of your design implementation cycle and drastically reduce the amount of effort you spend finding bugs later using time-consuming traditional test-bench methods.