Clock and Reset Domain Crossing Analysis
The Visual Verification Suite offers the capability to analyze and debug designs for Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) issues. The suite comes with a complete set of CDC and RDC analyses, an Advanced Clock Environment (ACE) for solving the iterative and reactive CDC setup problem, and a comprehensive set of debugging tools. Just like CDCs, the metastability induced by asynchronous RDCs cannot be modeled or exhaustively covered by digital simulation. Static analysis, up front as you design is critical to finding and eliminating issue before they become big problems.
- – Reduces metastability by finding improper synchronizers or clock domain groupings
- – Identifies FPGA clock generators and CDC synchronization and resets
- – IP block modeling reduces complexity and accommodates lack of model availability
- – Provides reports and schematics to understand and debug CDC and RDC synchronization issues
Ease of Setup
The suite’s Advanced Clock Environment (ACE) solves the iterative and reactive CDC setup problem experienced by designers. It is used before running a CDC analysis. With ACE, designers can clearly see if clocks are not in the intended domains and make corrections before in-depth CDC analysis.
- – Automatic Clock and reset identification
- – SDC input of domain information
- – Understands FPGA clock generator blocks to propagate clocks
- – Advanced clock analysis diagram
User Grey Cell (UGC) for IP-based Designs
In a typical flow, designers have to black box their generated or non-synthesizable IPs. The resulting CDC and RDC analysis is incomplete and does not report many CDC and RDC issues that lead to metastability in the field. With Blue Pearl’s User Grey Cell™ (UGC) methodology, CDC and RDC issues across boundary interfaces can be identified. Blue Pearl contains vendor UGC models and UGCs are easy to create from your databook.