News Archive ( 09/10/2018 ) HDL Creator Accelerates RTL and Test Bench Generation ( 11/06/2018 ) Blue Pearl Software to Unveil HDL Creator at the Design Automation Conference ( 16/04/2018 ) Blue Pearl Software Continues Rapid International Expansion with New Israeli Representative ( 29/03/2018 ) Blue Pearl Software Solutions Now Available in South Korea ( 26/03/2018 ) Blue Pearl Software Expands Japanese Presence with NeXtreamPartnership ( 08/11/2017 ) Blue Pearl Software’s CDC Analysis Just Got a Whole Lot Faster ( 21/07/2017 ) Blue Pearl Software Streamlines RTL Verification for Xilinx All Programmable FPGAs and SoCs ( 20/03/2017 ) Blue Pearl Software Collaborates with Microsemi to Accelerate FPGA Verification for Mil/Aero Designs ( 26/01/2017 ) Blue Pearl Software Unveils JumpStart Training and Consulting ( 11/15/2016 ) Blue Pearl Software Enters in to Agreement with FUJISOFT to Provide RTL Verification Solutions to Japan ( 06/02/2016 ) Blue Pearl Software Visual Verification Suite 2016.2 Simplifies ASIC, FPGA and IP RTL Verification ( 05/19/2016 ) Blue Pearl Software, Inc. Appoints New Representative for US, Western Region ( 05/19/2016 ) Blue Pearl Software, Inc. Appoints New Representative for UK and Ireland ( 06/07/2015 ) Blue Pearl Software Announces Release 9.1 Featuring New RTL Debugging Environment Including Formal Technology for Clock Domain Crossing (CDC) ( 05/21/2015 ) Blue Pearl Software announces new distributor for Turkey ( 04/03/2015 ) Barco Silex Standardizes on Blue Pearl Software – Transforms its ASIC and FPGA Design Flows ( 02/11/2015 ) Blue Pearl Software Introduces Debug Environment in Release 9.0 ( 12/09/2014 ) Verification Technology Inc. Transforms its FPGA Verification Flow by Standardizing on Blue Pearl Software. ( 05/27/2014 ) Blue Pearl Software Announces Release 8.1 with Advanced Clock Analysis. ( 12/06/2013 ) Blue Pearl Software Speeds Up FPGA Verification with Version 7.2. ( 09/27/2013 ) Blue Pearl Software Announces User Grey Cell™ Methodology with the Release of Version 7.1. ( 09/13/2013 ) Blue Pearl Software leads the way with online sales. ( 06/03/2013 ) Blue Pearl Software Suite is now available for purchase through Avnet/ARM Embedded Software Store. ( 06/03/2013 ) Blue Pearl Software Suite Customized for Xilinx Users. ( 05/21/2013 ) Blue Pearl Software joins Mentor OpenDoor Program. ( 05/16/2013 ) Blue Pearl Software opens Texas office. ( 04/30/2013 ) Blue Pearl Software appoints Murielle Lacombled as Sales Director, Southern Europe to support the growing demand for FPGA design tools. ( 04/18/2013 ) Blue Pearl Software announces new distributor for Taiwan. ( 04/01/2013 ) Blue Pearl Software names Roger Bitter Vice President, worldwide sales. ( 02/20/2013 ) Blue Pearl Advances FPGA RTL Signoff, Announces Release 6.2 with Enhanced Grey Cell Methodology. ( 02/07/2013 ) Blue Pearl Announces Expansion in China. ( 12/18/2012 ) Blue Pearl Announces North American Expansion. ( 12/13/2012 ) Blue Pearl Software Opens Japan Office and Appoints Katsuhiko Sakano as Sales Director to Support Growing Interest in FPGA Design Tools for Embedded Applications. ( 10/31/2012 ) At EDSFair, Blue Pearl Demos FPGA Design Tools for RTL Signoff, Presents on Overcoming Timing Challenges. ( 10/29/2012 ) Blue Pearl Demos FPGA Design Tools for RTL Signoff, Improves QoR at ARM TechCon. ( 10/24/2012 ) Blue Pearl Joins ARM® Connected Community®. ( 10/19/2012 ) Blue Pearl Software Advances FPGA Design Automation, Announces Software Release With Enhanced Path Analysis. ( 10/02/2012 ) Blue Pearl Software & Adacsys Present on Best FPGA Electronic Design Practices and Demonstrate Solutions. ( 08/01/2012 ) Blue Pearl Software Names Kavita Snyder VP of Worldwide Applications. ( 06/01/2012 ) Northwest Logic Uses Blue Pearl Software’s Analyze to Maximize IP Core Quality. ( 05/31/2012 ) At the 49th DAC, Blue Pearl Showcases Interoperability with Leading FPGA Ecosystem Players, Focuses on Accelerating FPGA Implementation. ( 05/30/2012 ) Blue Pearl Software’s Tool Experts to present at International Workshop on Logic and Synthesis. ( 05/29/2012 ) Blue Pearl Joins Xilinx Alliance Program, Accelerates Design Implementation. ( 04/06/2012 ) Blue Pearl Software Names Roger Bitter VP of International Sales. ( 03/13/2012 ) Blue Pearl Software Announces Support for Synopsys Synplify Pro Design Flow. ( 02/16/2012 ) Blue Pearl Announces Release 6.0 of EDA Software Suite with SystemVerilog and FPGA Enhancements. Chinese version: Blue Pearl Announces Release 6.0 of EDA Software Suite with SystemVerilog and FPGA Enhancements. ( 01/13/2012 ) Blue Pearl Software expands international presence with the addition of representatives in Europe and Asia. ( 12/13/2011 ) Blue Pearl Software’s Latest Release Exposed on GeekBeat and Available on Xuropa’s Cloud Platform ( 10/25/2011 ) Trilinear Technologies Shaves Weeks off Its Design Cycle with Blue Pearl’s Next Generation Software ( 6/22/2011 ) Sibridge Technologies Ensures Maximum IP Reliability with Blue Pearl’s Next Generation Software ( 1/27/2011 ) New Blue Pearl Suite Transforms IC Design Analysis, CDC Checking, SDC Creation and Validation ( 1/27/2011 ) Blue Pearl Software Names ATE Service Corporation Distributor for Japan ( 7/16/2009 ) Blue Pearl Software announces Create Timing Constraints™ Management (4/15/2009) Blue Pearl Software Announces Business Partnership Program with Electronic Design Service Companies and Consultants (1/21/2009) Blue Pearl Software Introduces “No EDA Tool Purchase Plan” (11/18/2008) Blue Pearl Software’s Version 4.0 of Create Timing Constraints™ Speeds-Up Timing Closure (3/31/2008) Blue Pearl Software Announces Validate Timing Constraints™ (7/24/2006) Beach Solutions and Blue Pearl Software Collaboration Ensures High Quality HDS Output of the Beach EASI Tool Suite HDL Generators. (7/18/2006) Blue Pearl Software Introduces Its Create Timing Constraints™ Software for Reducing Design Iterations and Risks in IC and IP Development (1/24/2005) Blue Pearl Software’s RTL Closure Tool Reduces Design Iterations and Improves Predictability (5/24/2004) Blue Pearl Software to Automate the Process of RTL Closure for IC and Electronic System Design EE Times ( 24-Jan-2005 ) “Blue Pearl Releases RTL Optimizer,” by Mike Santarini, published January 24, 2005 in * EE Times*. EE Times ( 24-May-2004 ) EDA startup Blue Pearl Software Inc. has announced the release of its first product, Analyze RTL™, for rapid functional closure. EE Times ( 24-May-2004 ) “EDA Start-up Blue Pearl preps trio of tools for ‘RTL Closure,” by Mike Santarini published May 24, 2004 in *EE Times. EE Times ( 24-May-2004 ) An EDA startup here promises to give ASIC, structured-ASIC and FPGA designers new ways to speed code through synthesis and, ultimately, all of chip design. Request Private Demo
HDL Creator Accelerates RTL and Test Bench Generation
Blue Pearl Software to Unveil HDL Creator at the Design Automation Conference
Blue Pearl Software Continues Rapid International Expansion with New Israeli Representative
Blue Pearl Software Solutions Now Available in South Korea
Blue Pearl Software Expands Japanese Presence with NeXtreamPartnership
Blue Pearl Software’s CDC Analysis Just Got a Whole Lot Faster
Blue Pearl Software Streamlines RTL Verification for Xilinx All Programmable FPGAs and SoCs
Blue Pearl Software Collaborates with Microsemi to Accelerate FPGA Verification for Mil/Aero Designs
Blue Pearl Software Unveils JumpStart Training and Consulting
Blue Pearl Software Enters in to Agreement with FUJISOFT to Provide RTL Verification Solutions to Japan
Blue Pearl Software Visual Verification Suite 2016.2 Simplifies ASIC, FPGA and IP RTL Verification
Blue Pearl Software, Inc. Appoints New Representative for US, Western Region
Blue Pearl Software, Inc. Appoints New Representative for UK and Ireland
Blue Pearl Software Announces Release 9.1 Featuring New RTL Debugging Environment Including Formal Technology for Clock Domain Crossing (CDC)
Blue Pearl Software announces new distributor for Turkey
Barco Silex Standardizes on Blue Pearl Software – Transforms its ASIC and FPGA Design Flows
Blue Pearl Software Introduces Debug Environment in Release 9.0
Verification Technology Inc. Transforms its FPGA Verification Flow by Standardizing on Blue Pearl Software.
Blue Pearl Software Announces Release 8.1 with Advanced Clock Analysis.
Blue Pearl Software Speeds Up FPGA Verification with Version 7.2.
Blue Pearl Software Announces User Grey Cell™ Methodology with the Release of Version 7.1.
Blue Pearl Software leads the way with online sales.
Blue Pearl Software Suite is now available for purchase through Avnet/ARM Embedded Software Store.
Blue Pearl Software Suite Customized for Xilinx Users.
Blue Pearl Software joins Mentor OpenDoor Program.
Blue Pearl Software opens Texas office.
Blue Pearl Software appoints Murielle Lacombled as Sales Director, Southern Europe to support the growing demand for FPGA design tools.
Blue Pearl Software announces new distributor for Taiwan.
Blue Pearl Software names Roger Bitter Vice President, worldwide sales.
Blue Pearl Advances FPGA RTL Signoff, Announces Release 6.2 with Enhanced Grey Cell Methodology.
Blue Pearl Announces Expansion in China.
Blue Pearl Announces North American Expansion.
Blue Pearl Software Opens Japan Office and Appoints Katsuhiko Sakano as Sales Director to Support Growing Interest in FPGA Design Tools for Embedded Applications.
At EDSFair, Blue Pearl Demos FPGA Design Tools for RTL Signoff,
Presents on Overcoming Timing Challenges.
Blue Pearl Demos FPGA Design Tools for RTL Signoff, Improves QoR at ARM TechCon.
Blue Pearl Joins ARM® Connected Community®.
Blue Pearl Software Advances FPGA Design Automation, Announces Software Release With Enhanced Path Analysis.
Blue Pearl Software & Adacsys Present on Best FPGA Electronic Design Practices and Demonstrate Solutions.
Blue Pearl Software Names Kavita Snyder VP of Worldwide Applications.
Northwest Logic Uses Blue Pearl Software’s Analyze to Maximize IP Core Quality.
At the 49th DAC, Blue Pearl Showcases Interoperability with Leading FPGA Ecosystem Players, Focuses on Accelerating FPGA Implementation.
Blue Pearl Software’s Tool Experts to present at International Workshop on Logic and Synthesis.
Blue Pearl Joins Xilinx Alliance Program, Accelerates Design Implementation.
Blue Pearl Software Names Roger Bitter VP of International Sales.
Blue Pearl Software Announces Support for Synopsys Synplify Pro Design Flow.
Blue Pearl Announces Release 6.0 of EDA Software Suite with SystemVerilog and FPGA Enhancements.
Blue Pearl Software expands international presence with the addition of representatives in Europe and Asia.
Blue Pearl Software’s Latest Release Exposed on GeekBeat and Available on Xuropa’s Cloud Platform
Trilinear Technologies Shaves Weeks off Its Design Cycle with Blue Pearl’s Next Generation Software
Sibridge Technologies Ensures Maximum IP Reliability with Blue Pearl’s Next Generation Software
New Blue Pearl Suite Transforms IC Design Analysis, CDC Checking, SDC Creation and Validation
Blue Pearl Software Names ATE Service Corporation Distributor for Japan
Blue Pearl Software announces Create Timing Constraints™ Management
Blue Pearl Software Announces Business Partnership Program with Electronic Design Service Companies and Consultants
Blue Pearl Software Introduces “No EDA Tool Purchase Plan”
Blue Pearl Software’s Version 4.0 of Create Timing Constraints™ Speeds-Up Timing Closure
Blue Pearl Software Announces Validate Timing Constraints™
Beach Solutions and Blue Pearl Software Collaboration Ensures High Quality HDS Output of the Beach EASI Tool Suite HDL Generators.
Blue Pearl Software Introduces Its Create Timing Constraints™ Software for Reducing Design Iterations and Risks in IC and IP Development
Blue Pearl Software’s RTL Closure Tool Reduces Design Iterations and Improves Predictability
Blue Pearl Software to Automate the Process of RTL Closure for IC and Electronic System Design
“Blue Pearl Releases RTL Optimizer,” by Mike Santarini, published January 24, 2005 in * EE Times*.
EDA startup Blue Pearl Software Inc. has announced the release of its first product, Analyze RTL™, for rapid functional closure.
“EDA Start-up Blue Pearl preps trio of tools for ‘RTL Closure,” by Mike Santarini published May 24, 2004 in *EE Times.
An EDA startup here promises to give ASIC, structured-ASIC and FPGA designers new ways to speed code through synthesis and, ultimately, all of chip design.